Processors (including, but not limited to, general and special purpose microprocessors, micro-controllers and Digital Signal Processors (DSPs)) typically include execution units that execute of sequence of instructions, termed micro-instructions, derived from a computer program. Many computer programs are written in a high-level language that is not directly executable by the central processing unit (CPU) of a computer and the instructions of such programs must accordingly be decoded into a form suitable for execution by the CPU. For example, a program may be written in a high-level language such as C, C++ or Java, and then complied into a corresponding sequence of macro-instructions, which are in turn decoded into micro-instructions for eventual execution. Programs can of course be written directly as a series of macro-instructions (i.e., machine code).
Macro-instructions are commonly stored as contiguous data blocks in a memory resource, such as main memory (e.g., RAM) or in a cache, for retrieval and supply to a decoder unit within a processor for decoding into micro-instructions. To enable the decoder unit successfully to decode macro-instructions, it will be appreciated that is necessary to identify instruction boundaries within retrieved data blocks, that constitute the instruction stream, that indicate where one macro-instruction ends and the next begins.
The task of identifying such instruction boundaries by processors having Complex Instruction Set Computer (CISC) architectures, such as the Intel Architecture (IA) developed by Intel Corporation of Santa Clara, Calif., is complicated by the use of a variable-length instruction set (e.g., the Intel Architecture (IA) instruction set). Specifically, in Reduced Instruction Set Computer (RISC) processor architectures and instruction sets, macro-instructions typically have a fixed length, in which case the boundaries between instructions can be determined with relative ease once an initial boundary is identified, as each instruction has a known length. For a variable-length instruction set, once an initial boundary location is identified, the length of each macro-instruction must be ascertained to identify subsequent instruction boundaries. The task of identifying boundaries is further complicated by a variable-length instruction set that, for the purposes of supporting legacy programs, supports multiple data and addressing sizes. For example, this capability is achieved in the IA instruction set by the use of length-changing prefixes that alter the address and operand sizes (or lengths) of instructions from 16 to 32 bits, and vice versa.